Attiny1624-ring

Alphabets V2 ATtiny1624 ring module

This directory contains the editable KiCad 10 design for one Alphabets V2 split-flap module. The board keeps the existing 2x3 synchronous-ring connector, drives an external four-input stepper board, reads a powered HOME sensor, and uses the ATtiny1624's one-wire UPDI programming interface.

The hardware assignment follows Microchip's ATtiny1624/1626/1627 data sheet. Microchip documents PA0 as UPDI/RESET and PA1, PA2, and PA3 as SPI0 MOSI, MISO, and SCK respectively. The standard programming connection is the 2x3, 2.54 mm UPDI header described in Microchip's UPDI connection guide.

Circuit

• U1: ATtiny1624-SSU in SOIC-14.
• J1: 2x3 SMD ring connector for LATCH, CLOCK, serial data, +5 V, and GND.
• J3: four logic outputs for the external stepper driver.
• J4: powered three-pin HOME sensor connector with a 10 kOhm pull-up.
• J5: 2x3 SMD UPDI connector; pins 1, 2, and 6 carry UPDI, target VDD, and GND. Pins 3 through 5 are intentionally not connected.
• R1: 10 kOhm UPDI pull-up; R2: 10 kOhm HOME pull-up.
• C1: 100 nF local MCU decoupling; C2: 1 nF high-frequency bypass; C3: 10 uF board bulk capacitance.
• JP1 through JP4, JP6, and JP9: removable 0 Ohm 1206 links that partition power, ground, and ring signals for assembly and diagnosis.

The board defines this ATtiny1624 signal assignment:

PA6 and PA7 remain available and are intentionally not connected in this revision. The matching firmware and host-side protocol tests are in ATtiny1624 module firmware.

Connectors

The chain connector follows the module protocol: pins 1, 2, 4, and 6 are bused, while pin 5 of one module feeds pin 3 of the next module.

Single-sided construction

• Finished outline: 50 x 50 mm.
• All routed copper is on F.Cu; the design contains no vias or back-copper tracks.
• Preferred tracks are 20 mil (0.508 mm). Constrained neckdowns are 16 mil (0.4064 mm), above the 15 mil minimum.
• Copper clearance is 0.40 mm for a 0.40 mm milling tool.
• Corners use native KiCad arcs with adaptive radii from 0.20 to 2.00 mm.
• Width transitions use curved copper tapers and routed SMD entries use curved teardrops.
• Every discrete resistor and capacitor uses a hand-solderable 1206 footprint.

Ten insulated wire links cross above the routed copper. Solder insulated wire between the two pads of each footprint; the dashed F.Fab line marks its assembly path and is not copper:

Files and reproducible validation

• attiny1624-ring.kicad_pro, .kicad_sch, and .kicad_pcb: editable native KiCad project files.
• fabrication/: Gerbers, drill outputs, BOM, positions, and STEP model.
• preview/: top render, front-copper drawing, and schematic drawing.
• validation/: ERC and DRC/schematic-parity reports.
• routing/attiny1624-ring.ses: checked-in single-layer routing session.
• tools/: deterministic generators, route import, organic post-processing, and project-specific electrical/mechanical checks.

The normal reproducible path starts from the checked-in route:

make schematic board route organic check fabrication previews

Set KICAD_CLI, KICAD_PYTHON, KIUTILS_PYTHON, and KICAD10_FOOTPRINT_DIR for the installed KiCad environment. When placement or the netlist changes, create a new session with:

make autoroute FREEROUTING_JAR=/path/to/freerouting.jar

make check enforces the 50 x 50 mm outline, front-copper-only routing, zero vias, 16/20 mil widths, ten wire links, native arcs, teardrops, zero ERC/DRC violations, zero unrouted connections, and exact schematic-to-PCB parity.