4 layers28.7 × 26 mm
Minifoc esc
murexrobotics/electrical
Highly integrated electronics design and printed circuit boards (PCBs) for the MATE ROV Competition. Attempt the impossible.
53 parts192MIT
4 layers50 × 85 mm
Pcie analyzer
PavlenkoG/ECP5_PCIE_Analyzer17https://www.latticesemi.com/products/developmentboardsandkits/ecp5evaluationboard # VERSA Expansion Headers # Eval Board top view
- Size
- 50 × 85 mm
- Copper layers
- 4
- Thickness
- 1.6 mm
- Parts
- 53
- Nets
- 100
- Pads
- 253
- Tracks, vias
- 415, 122
- Pours
- 6
- Routed
- Yes
- KiCad
- KiCad 5 (file 20171130)
- Created
- 6 Aug 2021
- Updated
- 6 Oct 2023
Overview
Pcie analyzer is an open-source printed circuit board by PavlenkoG, from the PavlenkoG/ECP5_PCIE_Analyzer repository on GitHub. It is a 4-layer board of 50 × 85 mm with 53 parts on 100 nets, routed with 415 tracks and 122 vias.
Its parts include 27 capacitors, 11 resistors, 8 connectors and 3 diodes. It belongs with the sensors and measurement and computers and single-board computers boards of this library.
README
README.mdECP5_PCIE_Analyzer
The main idea of this project is the evaluation of the possibility of using the PCS-Block of ECP5UMG FPGA for PCI-Express protocol analysis. The PCS Block can deserialize physical PCI-Express signals and decode 8b10b.
Deserialized data can be used to analyze protocol traffic, detecting errors and so on.
The first implementation involves an adapter print to connect PCI-Express lanes to PCS-Block in FPGA and an evaluation board with ECP5UM(G).
The adapter print should be connected to the eval. board through VERSA Expansion headers and SMA-Cables.
https://www.latticesemi.com/products/developmentboardsandkits/ecp5evaluationboard
VERSA Expansion Headers
Eval Board top view
Eval Board bottom view
PCB
Preparing for applying solder paste
Mounting of SMT Stencil
Applying solder paste
PCB
PCB with solder paste
Mounted PCB
Python script usage
record data (on raspberry pi)
pi@raspberrypi:~/github/ECP5_PCIE_Analyzer/py_script $ python3 analyzer.py
['analyzer.py']
file removed
Time: 11.82167429399999 sanalyze data
copy data to local
scp -r pi@192.168.178.29:~/github/ECP5_PCIE_Analyzer/py_script/*.csv .Parts
53| Qty | Value | Footprint | References |
|---|---|---|---|
| 12 | 0.1u | ecp5_pcie_analyzer:C_0402 | C8, C10, C12, C14, C16, C18, C22, C23, C24, C25, C26, C27 |
| 9 | 100n | ecp5_pcie_analyzer:C_0402 | C4, C5, C6, C13, C15, C17, C19, C20, C21 |
| 6 | 1n | ecp5_pcie_analyzer:C_0402 | C1, C2, C3, C7, C9, C11 |
| 6 | Conn_Coaxial | ecp5_pcie_analyzer:SMA_Amphenol_132291_Vertical | J3, J4, J5, J6, J7, J8 |
| 5 | 0 | ecp5_pcie_analyzer:R_0402 | R4, R5, R6, R10, R11 |
| 3 | 10K | ecp5_pcie_analyzer:R_0402 | R7, R8, R9 |
| 3 | 4.75K | ecp5_pcie_analyzer:R_0402 | R1, R2, R3 |
| 3 | Ferrite_Bead | ecp5_pcie_analyzer:FB_0402 | FB1, FB2, FB3 |
| 3 | ONET1191P | ecp5_pcie_analyzer:VQFN-16 | D1, D2, D3 |
| 2 | HDR40 | ecp5_pcie_analyzer:SAMTEC_TSW-120-05-G-D | J1, J2 |
| 1 | AXIAL_CABLE_SL8800_08 | ecp5_pcie_analyzer:AXIAL_CABLE_SL8800_08 | ST1 |
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Questions
How big is the Pcie analyzer PCB?
It measures 50 × 85 mm and has 4 copper layers, 1.6 mm thick.
What parts does the Pcie analyzer use?
53 parts. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Pcie analyzer KiCad files?
From the PavlenkoG/ECP5_PCIE_Analyzer repository on GitHub, at the commit this page was made from: the board is hardware/main/pcie_analyzer/pcie_analyzer.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Can I use the Pcie analyzer design in my own project?
Its repository states no licence, so its author keeps all rights: ask PavlenkoG before reusing the design.